(ABI) JTAG Master Boundary Scan Tester and Programmer
문자 물품문의 ☎ 첨단마켓관리자 문의: 02-3142-4151
- 제조년월
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- 재고상황
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- 세금계산서
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- A/S정보
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JTAGMaster는 프로그램가능 논리소자(PLD)의 구성 및 진단을 위한 통합된 솔루션입니다.
제조상의 결함, 로직 오류, 프로그래머 오류, 외부 연결회로 상에서의 고장 검출 기능 등을 제공합니다.
- No technical knowledge needed
- Boundary scan testing
- Integrated JAM/SVF Player for programming
- Automatic detection of JTAG chains
- Automatic training function
- JTAG/IEEE 1149.1 compatible
- USB2.0 compatible
- Built-in power supply (1.8 to 3.3 Volts)
JTAGMaster Boundary Scan Tester and Programmer
The JTAGMaster Tester and Programmer is a fully integrated solution for the configuration and diagnosis of Programmable Logic Devices (PLDs). This unit includes :
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A boundary-scan tester to arbitrarily observe individual pins and therefore determine their functionality. This information can be saved in customisable test procedures which can also include pictures and datasheets. EXTEST mode is also available to manually change the state of pins and trace the effect(s) on the other device(s) in the chain. Scan Check is a multi-license software to run boundary scan checks on multiple stations.
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A programming interface designed to handle industry standard JAM STAPL files (Standard Test And Programming Language) and SVF files (Serial Vector Format) to send programming instructions as well as testing functions to the device. ABI uses the JTAG Standards (Joint Test Action Group, compatible with IEEE1149.1) which ensures compatibility between all compliant ICs.
The JTAGMaster is also capable of programming EEPROM devices using external adapters. Standard brinary files are supported and can also be modified in the device buffer window. A wide range of EEPROM devices are present in the library which can be easily modified by users. The following protocols are supported by the JTAGMaster :
- Serial Peripheral Interface (SPI)
- Inter-Integrated Circuit (I²C)
- Microwire (μwire)
As a product, the JTAGMaster In-System and Standalone Programmer is also available.
Please click here to view the complete brochure.
The JTAGMaster Tester and Programmer is designed to work with ABI’s bespoke software - a multiple purpose platform which enables users to freely configure test procedures and instruments. Integrated functions are also available to the user to automatically learn the device status, provide pin-to-pin comparison and information as well as use some reporting facilities. The internal library can be updated through BSDL files available from manufacturers' websites (see below).
With its ability to both test and program PLDs, this new ABI product allows users to verify the functionality of a device, download a bespoke program to a device or even re-test the device after it has been programmed !
A complete training package for the JTAGMaster is also available - please click here for more information.
Video Presentation
A more detailed presentation video is available here. |
Boundary Scan Description Language (BSDL)
Boundary Scan Description Language (BSDL) is a subset of VHDL that is used to describe how JTAG (IEEE 1149.1) is implemented in a particular device. For a device to be JTAG compliant, it must have an associated BSDL file. These files are often available for download from manufacturers' websites (see below). JTAG systems uses the information contained in a BSDL file to work out how to access a device in the JTAG chain. BSDL files contain the following elements:
- Entity Description: Statements naming the device or a section of its functionality.
- Generic Parameter: A value such as a package type. The value may come from outside the current entity.
- Port Description: Describes the nature of the pins on the device (input, output, bidirectional, linkage).
- Use Statements: References external definitions (such as IEEE 1149.1).
- Pin Mapping(s): Maps logical signals in the device to physical pins.
- Scan Port Identification: Defines the pins used on the device to access the JTAG capabilities.
- Instruction Register Description: The signals used for accessing JTAG device modes.
- Register Access Description: Which register is placed between TDI and TDO for each JTAG instruction.
- Boundary Register Description: List of the boundary scan cells and their functionality
Download BSDL files for your JTAG components:
Further information available at BSDL Files Library.
Features
- Boundary scan testing
- Integrated JAM/SVF Player for programming
- Automatic detection of JTAG chains
- Automatic training function
- JTAG/IEEE 1149.1 compatible
- USB2.0 compatible
- Built-in power supply (1.8 to 3.3 Volts)
Technical Specifications
Electrical Requirements
Physical Specifications
Environmental Requirements
Comprehensive Training Package (optional) |
Computer Requirements
Included Accessories
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판매사 정보
판매사 | 인코어테크놀로지(주) | 홈페이지 | http://www.incoretech.co.kr |
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구매문의 | 070-8670-2130 | 이메일 | sales@incoretech.co.kr |
사업장소재지 | 서울 성동구 성수동2가 309-126 3층 |
판매사 다른 상품
판매사 정보
상호/대표자 | 인코어테크놀로지(주) / 홍경표 | 사업자등록번호 | 206-86-56708 | |
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사업장소재지 | 서울 성동구 성수동2가 309-126 3층 | |||
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상품고시 품목별정보
상품정보제공고시
품명 및 모델명 | (ABI) JTAG Master Boundary Scan Tester and Programmer / JTAG Master Boundary Scan Tester and Programmer |
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제조국 또는 원산지 | |
제조사/판매사 | 인코어테크놀로지(주) |
구매문의 | 070-8670-2130 |
상품상태 | 신제품 |
A/S정보 | 가능 |
제조년월 | |
부가가치세 | 가세 |
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